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Changed the XPLAINBridge software UART to use the regular CTC mode instead of the alternative CTC mode via the Input Capture register, to reduce user confusion.

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This commit is contained in:
Dean Camera
2010-11-25 03:20:01 +00:00
parent fd77bf5c94
commit b634ec50a0
4 changed files with 12 additions and 11 deletions
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Projects/XPLAINBridge/Lib/SoftUART.c
+6 -6
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@@ -67,11 +67,11 @@ void SoftUART_Init(void)
SoftUART_SetBaud(9600);
/* Setup reception timer compare ISR */
TIMSK1 = (1 << ICIE1);
TIMSK1 = (1 << OC1E1A);
/* Setup transmission timer compare ISR and start the timer */
TIMSK3 = (1 << ICIE3);
TCCR3B = ((1 << CS30) | (1 << WGM33) | (1 << WGM32));
TIMSK3 = (1 << OC1E3A);
TCCR3B = ((1 << CS30) | (1 << WGM32));
}
/** ISR to detect the start of a bit being sent to the software UART. */
@@ -90,12 +90,12 @@ ISR(INT0_vect, ISR_BLOCK)
EIMSK = 0;
/* Start the reception timer */
TCCR1B = ((1 << CS10) | (1 << WGM13) | (1 << WGM12));
TCCR1B = ((1 << CS10) | (1 << WGM12));
}
}
/** ISR to manage the reception of bits to the software UART. */
ISR(TIMER1_CAPT_vect, ISR_BLOCK)
ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{
/* Cache the current RX pin value for later checking */
uint8_t SRX_Cached = (SRXPIN & (1 << SRX));
@@ -125,7 +125,7 @@ ISR(TIMER1_CAPT_vect, ISR_BLOCK)
}
/** ISR to manage the transmission of bits via the software UART. */
ISR(TIMER3_CAPT_vect, ISR_BLOCK)
ISR(TIMER3_COMPA_vect, ISR_BLOCK)
{
/* Check if transmission has finished */
if (TX_BitsRemaining)